In a semiconductor memory device with built-in memory chips such as a NAND type flash memory, miniaturization and high capacity have advanced rapidly. In a semiconductor memory device, in order to achieve both miniaturization and high capacity, a plurality of memory chips are sequentially stacked on a wiring substrate, and these semiconductor chips are sealed with a resin layer. To reduce the thickness of such a semiconductor device, the thickness of the sealing resin layer on the semiconductor chips is minimized. Such minimization can cause warping during heat treatment such as a solder reflow process.
The resin layer generally warps such that the upper surface of the resin layer is convex at room temperature and concave at elevated temperature. Reducing thickness of the resin layer increases warping, particularly at elevated temperatures. Warping can be suppressed by adjusting properties of the sealing resin, properties of the substrate material, or thickness of the substrate. However, such adjustments increase material cost or substrate cost. In addition, in some cases, needed warp suppression is not available within tolerance merely by adjusting material properties or thickness of the substrate. Therefore, a cost-effective technology is needed that can suppress warping of a semiconductor device.